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ppcopc.cc

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00001 /*
00002  *      HT Editor
00003  *      ppcopc.cc
00004  *
00005  *      Copyright (C) 1999-2002 Sebastian Biallas (sb@web-productions.de)
00006  *      Copyright 1994 Free Software Foundation, Inc.
00007  *      Written by Ian Lance Taylor, Cygnus Support
00008  *
00009  *      This program is free software; you can redistribute it and/or modify
00010  *      it under the terms of the GNU General Public License version 2 as
00011  *      published by the Free Software Foundation.
00012  *
00013  *      This program is distributed in the hope that it will be useful,
00014  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
00015  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016  *      GNU General Public License for more details.
00017  *
00018  *      You should have received a copy of the GNU General Public License
00019  *      along with this program; if not, write to the Free Software
00020  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
00021  */
00022 
00023 #include "ppcopc.h"
00024 
00025 /* The functions used to insert and extract complicated operands.  */
00026 
00027 /* The BA field in an XL form instruction when it must be the same as
00028    the BT field in the same instruction.  This operand is marked FAKE.
00029    The insertion function just copies the BT field into the BA field,
00030    and the extraction function just checks that the fields are the
00031    same.  */
00032 
00033 static uint32 extract_bat(uint32 insn, bool *invalid)
00034 {
00035         if (invalid != NULL && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) *invalid = 1;
00036         return 0;
00037 }
00038 
00039 /* The BB field in an XL form instruction when it must be the same as
00040    the BA field in the same instruction.  This operand is marked FAKE.
00041    The insertion function just copies the BA field into the BB field,
00042    and the extraction function just checks that the fields are the
00043    same.  */
00044 
00045 static uint32 extract_bba(uint32 insn, bool *invalid)
00046 {
00047         if (invalid != NULL && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) *invalid = 1;
00048         return 0;
00049 }
00050 
00051 /* The BD field in a B form instruction.  The lower two bits are
00052    forced to zero.  */
00053 
00054 
00055 static uint32 extract_bd(uint32 insn, bool *invalid)
00056 {
00057         if ((insn & 0x8000) != 0) {
00058                 return (insn & 0xfffc) - 0x10000;
00059         } else {
00060                 return insn & 0xfffc;
00061         }
00062 }
00063 
00064 /* The BD field in a B form instruction when the - modifier is used.
00065    This modifier means that the branch is not expected to be taken.
00066    We must set the y bit of the BO field to 1 if the offset is
00067    negative.  When extracting, we require that the y bit be 1 and that
00068    the offset be positive, since if the y bit is 0 we just want to
00069    print the normal form of the instruction.  */
00070 
00071 static uint32 extract_bdm(uint32 insn, bool *invalid)
00072 {
00073         if (invalid != NULL && ((insn & (1 << 21)) == 0 || (insn & (1 << 15)) == 0)) *invalid = 1;
00074         if ((insn & 0x8000) != 0) {
00075                 return (insn & 0xfffc) - 0x10000;
00076         } else {
00077                 return insn & 0xfffc;
00078         }
00079 }
00080 
00081 /* The BD field in a B form instruction when the + modifier is used.
00082    This is like BDM, above, except that the branch is expected to be
00083    taken.  */
00084 
00085 static uint32 extract_bdp(uint32 insn, bool *invalid)
00086 {
00087         if (invalid != NULL && ((insn & (1 << 21)) == 0 || (insn & (1 << 15)) != 0)) *invalid = 1;
00088         if ((insn & 0x8000) != 0) {
00089                 return (insn & 0xfffc) - 0x10000;
00090         } else {
00091                 return insn & 0xfffc;
00092         }
00093 }
00094 
00095 /* Check for legal values of a BO field.  */
00096 
00097 static int valid_bo(uint32 value)
00098 {
00099         /* Certain encodings have bits that are required to be zero.  These
00100            are (z must be zero, y may be anything):
00101            001zy
00102            011zy
00103            1z00y
00104            1z01y
00105            1z1zz
00106          */
00107         switch (value & 0x14) {
00108                 default:
00109                 case 0:
00110                         return 1;
00111                 case 0x4:
00112                         return (value & 0x2) == 0;
00113                 case 0x10:
00114                         return (value & 0x8) == 0;
00115                 case 0x14:
00116                         return value == 0x14;
00117         }
00118 }
00119 
00120 /* The BO field in a B form instruction.  Warn about attempts to set
00121    the field to an illegal value.  */
00122 
00123 static uint32 extract_bo(uint32 insn, bool *invalid)
00124 {
00125         uint32 value;
00126 
00127         value = (insn >> 21) & 0x1f;
00128         if (invalid != NULL && ! valid_bo (value))
00129         *invalid = 1;
00130         return value;
00131 }
00132 
00133 /* The BO field in a B form instruction when the + or - modifier is
00134    used.  This is like the BO field, but it must be even.  When
00135    extracting it, we force it to be even.  */
00136    
00137 static uint32 extract_boe(uint32 insn, bool *invalid)
00138 {
00139         uint32 value;
00140 
00141         value = (insn >> 21) & 0x1f;
00142         if (invalid != NULL && ! valid_bo (value)) *invalid = 1;
00143         return value & 0x1e;
00144 }
00145 
00146 /* The DS field in a DS form instruction.  This is like D, but the
00147    lower two bits are forced to zero.  */
00148 
00149 
00150 static uint32 extract_ds(uint32 insn, bool *invalid)
00151 {
00152         if ((insn & 0x8000) != 0) {
00153                 return (insn & 0xfffc) - 0x10000;
00154         } else {
00155                 return insn & 0xfffc;
00156         }
00157 }
00158 
00159 /* The LI field in an I form instruction.  The lower two bits are
00160    forced to zero.  */
00161 
00162 
00163 static uint32 extract_li(uint32 insn, bool *invalid)
00164 {
00165         if ((insn & 0x2000000) != 0) {
00166                 return (insn & 0x3fffffc) - 0x4000000;
00167         } else {
00168                 return insn & 0x3fffffc;
00169         }
00170 }
00171 
00172 /* The MB and ME fields in an M form instruction expressed as a single
00173    operand which is itself a bitmask.  The extraction function always
00174    marks it as invalid, since we never want to recognize an
00175    instruction which uses a field of this type.  */
00176 
00177 static uint32 extract_mbe(uint32 insn, bool *invalid)
00178 {
00179         uint32 ret;
00180         int mb, me;
00181         int i;
00182 
00183         if (invalid != NULL) *invalid = 1;
00184 
00185         ret = 0;
00186         mb = (insn >> 6) & 0x1f;
00187         me = (insn >> 1) & 0x1f;
00188         for (i = mb; i < me; i++) ret |= 1 << (31 - i);
00189         return ret;
00190 }
00191 
00192 /* The MB or ME field in an MD or MDS form instruction.  The high bit
00193    is wrapped to the low end.  */
00194 
00195 
00196 static uint32 extract_mb6(uint32 insn, bool *invalid)
00197 {
00198         return ((insn >> 6) & 0x1f) | (insn & 0x20);
00199 }
00200 
00201 /* The NB field in an X form instruction.  The value 32 is stored as
00202    0.  */
00203 
00204 
00205 static uint32 extract_nb(uint32 insn, bool *invalid)
00206 {
00207         uint32 ret;
00208 
00209         ret = (insn >> 11) & 0x1f;
00210      if (ret == 0) ret = 32;
00211         return ret;
00212 }
00213 
00214 /* The NSI field in a D form instruction.  This is the same as the SI
00215    field, only negated.  The extraction function always marks it as
00216    invalid, since we never want to recognize an instruction which uses
00217    a field of this type.  */
00218 
00219 static uint32 extract_nsi(uint32 insn, bool *invalid)
00220 {
00221         if (invalid != NULL) *invalid = 1;
00222         if ((insn & 0x8000) != 0) {
00223                 return - ((insn & 0xffff) - 0x10000);
00224         } else {
00225                 return - (insn & 0xffff);
00226         }
00227 }
00228 
00229 /* The RA field in a D or X form instruction which is an updating
00230    load, which means that the RA field may not be zero and may not
00231    equal the RT field.  */
00232 
00233 /* The RB field in an X form instruction when it must be the same as
00234    the RS field in the instruction.  This is used for extended
00235    mnemonics like mr.  This operand is marked FAKE.  The insertion
00236    function just copies the BT field into the BA field, and the
00237    extraction function just checks that the fields are the same.  */
00238 
00239 static uint32 extract_rbs(uint32 insn, bool *invalid)
00240 {
00241   if (invalid != NULL
00242       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
00243     *invalid = 1;
00244   return 0;
00245 }
00246 
00247 /* The SH field in an MD form instruction.  This is split.  */
00248 
00249 static uint32 extract_sh6(uint32 insn, bool *invalid)
00250 {
00251   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
00252 }
00253 
00254 /* The SPR field in an XFX form instruction.  This is flipped--the
00255    lower 5 bits are stored in the upper 5 and vice- versa.  */
00256 
00257 static uint32 extract_spr(uint32 insn, bool *invalid)
00258 {
00259   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
00260 }
00261 
00262 /* The TBR field in an XFX instruction.  This is just like SPR, but it
00263    is optional.  When TBR is omitted, it must be inserted as 268 (the
00264    magic number of the TB register).  These functions treat 0
00265    (indicating an omitted optional operand) as 268.  This means that
00266    ``mftb 4,0'' is not handled correctly.  This does not matter very
00267    much, since the architecture manual does not define mftb as
00268    accepting any values other than 268 or 269.  */
00269 
00270 #define TB (268)
00271 
00272 static uint32 extract_tbr(uint32 insn, bool *invalid)
00273 {
00274   uint32 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
00275   if (ret == TB) ret = 0;
00276   return ret;
00277 }
00278 
00279 /* The operands table.
00280 
00281    The fields are bits, shift, signed, extract, flags.  */
00282 
00283 const struct powerpc_operand powerpc_operands[] =
00284 {
00285   /* The zero index is used to indicate the end of the list of
00286      operands.  */
00287 #define UNUSED (0)
00288   { 0, 0, 0, 0 },
00289 
00290   /* The BA field in an XL form instruction.  */
00291 #define BA (1)
00292 #define BA_MASK (0x1f << 16)
00293   { 5, 16, 0, PPC_OPERAND_CR },
00294 
00295   /* The BA field in an XL form instruction when it must be the same
00296      as the BT field in the same instruction.  */
00297 #define BAT (2)
00298   { 5, 16, extract_bat, PPC_OPERAND_FAKE },
00299 
00300   /* The BB field in an XL form instruction.  */
00301 #define BB (3)
00302 #define BB_MASK (0x1f << 11)
00303   { 5, 11, 0, PPC_OPERAND_CR },
00304 
00305   /* The BB field in an XL form instruction when it must be the same
00306      as the BA field in the same instruction.  */
00307 #define BBA (4)
00308   { 5, 11, extract_bba, PPC_OPERAND_FAKE },
00309 
00310   /* The BD field in a B form instruction.  The lower two bits are
00311      forced to zero.  */
00312 #define BD (5)
00313   { 16, 0, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00314 
00315   /* The BD field in a B form instruction when absolute addressing is
00316      used.  */
00317 #define BDA (6)
00318   { 16, 0, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00319 
00320   /* The BD field in a B form instruction when the - modifier is used.
00321      This sets the y bit of the BO field appropriately.  */
00322 #define BDM (7)
00323   { 16, 0, extract_bdm, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00324 
00325   /* The BD field in a B form instruction when the - modifier is used
00326      and absolute address is used.  */
00327 #define BDMA (8)
00328   { 16, 0, extract_bdm, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00329 
00330   /* The BD field in a B form instruction when the + modifier is used.
00331      This sets the y bit of the BO field appropriately.  */
00332 #define BDP (9)
00333   { 16, 0, extract_bdp, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00334 
00335   /* The BD field in a B form instruction when the + modifier is used
00336      and absolute addressing is used.  */
00337 #define BDPA (10)
00338   { 16, 0, extract_bdp, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00339 
00340   /* The BF field in an X or XL form instruction.  */
00341 #define BF (11)
00342   { 3, 23, 0, PPC_OPERAND_CR },
00343 
00344   /* An optional BF field.  This is used for comparison instructions,
00345      in which an omitted BF field is taken as zero.  */
00346 #define OBF (12)
00347   { 3, 23, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
00348 
00349   /* The BFA field in an X or XL form instruction.  */
00350 #define BFA (13)
00351   { 3, 18, 0, PPC_OPERAND_CR },
00352 
00353   /* The BI field in a B form or XL form instruction.  */
00354 #define BI (14)
00355 #define BI_MASK (0x1f << 16)
00356   { 5, 16, 0, PPC_OPERAND_CR },
00357 
00358   /* The BO field in a B form instruction.  Certain values are
00359      illegal.  */
00360 #define BO (15)
00361 #define BO_MASK (0x1f << 21)
00362   { 5, 21, extract_bo, 0 },
00363 
00364   /* The BO field in a B form instruction when the + or - modifier is
00365      used.  This is like the BO field, but it must be even.  */
00366 #define BOE (16)
00367   { 5, 21, extract_boe, 0 },
00368 
00369   /* The BT field in an X or XL form instruction.  */
00370 #define BT (17)
00371   { 5, 21, 0, PPC_OPERAND_CR },
00372 
00373   /* The condition register number portion of the BI field in a B form
00374      or XL form instruction.  This is used for the extended
00375      conditional branch mnemonics, which set the lower two bits of the
00376      BI field.  This field is optional.  */
00377 #define CR (18)
00378   { 3, 18, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
00379 
00380   /* The D field in a D form instruction.  This is a displacement off
00381      a register, and implies that the next operand is a register in
00382      parentheses.  */
00383 #define D (19)
00384   { 16, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
00385 
00386   /* The DS field in a DS form instruction.  This is like D, but the
00387      lower two bits are forced to zero.  */
00388 #define DS (20)
00389   { 16, 0, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
00390 
00391   /* The FL1 field in a POWER SC form instruction.  */
00392 #define FL1 (21)
00393   { 4, 12, 0, 0 },
00394 
00395   /* The FL2 field in a POWER SC form instruction.  */
00396 #define FL2 (22)
00397   { 3, 2, 0, 0 },
00398 
00399   /* The FLM field in an XFL form instruction.  */
00400 #define FLM (23)
00401   { 8, 17, 0, 0 },
00402 
00403   /* The FRA field in an X or A form instruction.  */
00404 #define FRA (24)
00405 #define FRA_MASK (0x1f << 16)
00406   { 5, 16, 0, PPC_OPERAND_FPR },
00407 
00408   /* The FRB field in an X or A form instruction.  */
00409 #define FRB (25)
00410 #define FRB_MASK (0x1f << 11)
00411   { 5, 11, 0, PPC_OPERAND_FPR },
00412 
00413   /* The FRC field in an A form instruction.  */
00414 #define FRC (26)
00415 #define FRC_MASK (0x1f << 6)
00416   { 5, 6, 0, PPC_OPERAND_FPR },
00417 
00418   /* The FRS field in an X form instruction or the FRT field in a D, X
00419      or A form instruction.  */
00420 #define FRS (27)
00421 #define FRT (FRS)
00422   { 5, 21, 0, PPC_OPERAND_FPR },
00423 
00424   /* The FXM field in an XFX instruction.  */
00425 #define FXM (28)
00426 #define FXM_MASK (0xff << 12)
00427   { 8, 12, 0, 0 },
00428 
00429   /* The L field in a D or X form instruction.  */
00430 #define L (29)
00431   { 1, 21, 0, PPC_OPERAND_OPTIONAL },
00432 
00433   /* The LEV field in a POWER SC form instruction.  */
00434 #define LEV (30)
00435   { 7, 5, 0, 0 },
00436 
00437   /* The LI field in an I form instruction.  The lower two bits are
00438      forced to zero.  */
00439 #define LI (31)
00440   { 26, 0, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00441 
00442   /* The LI field in an I form instruction when used as an absolute
00443      address.  */
00444 #define LIA (32)
00445   { 26, 0, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00446 
00447   /* The MB field in an M form instruction.  */
00448 #define MB (33)
00449 #define MB_MASK (0x1f << 6)
00450   { 5, 6, 0, 0 },
00451 
00452   /* The ME field in an M form instruction.  */
00453 #define ME (34)
00454 #define ME_MASK (0x1f << 1)
00455   { 5, 1, 0, 0 },
00456 
00457   /* The MB and ME fields in an M form instruction expressed a single
00458      operand which is a bitmask indicating which bits to select.  This
00459      is a two operand form using PPC_OPERAND_NEXT.  See the
00460      description in opcode/ppc.h for what this means.  */
00461 #define MBE (35)
00462   { 5, 6, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
00463   { 32, 0, extract_mbe, 0 },
00464 
00465   /* The MB or ME field in an MD or MDS form instruction.  The high
00466      bit is wrapped to the low end.  */
00467 #define MB6 (37)
00468 #define ME6 (MB6)
00469 #define MB6_MASK (0x3f << 5)
00470   { 6, 5, extract_mb6, 0 },
00471 
00472   /* The NB field in an X form instruction.  The value 32 is stored as
00473      0.  */
00474 #define NB (38)
00475   { 6, 11, extract_nb, 0 },
00476 
00477   /* The NSI field in a D form instruction.  This is the same as the
00478      SI field, only negated.  */
00479 #define NSI (39)
00480   { 16, 0, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
00481 
00482   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
00483 #define RA (40)
00484 #define RA_MASK (0x1f << 16)
00485   { 5, 16, 0, PPC_OPERAND_GPR },
00486 
00487   /* The RA field in a D or X form instruction which is an updating
00488      load, which means that the RA field may not be zero and may not
00489      equal the RT field.  */
00490 #define RAL (41)
00491   { 5, 16, 0, PPC_OPERAND_GPR },
00492 
00493   /* The RA field in an lmw instruction, which has special value
00494      restrictions.  */
00495 #define RAM (42)
00496   { 5, 16, 0, PPC_OPERAND_GPR },
00497 
00498   /* The RA field in a D or X form instruction which is an updating
00499      store or an updating floating point load, which means that the RA
00500      field may not be zero.  */
00501 #define RAS (43)
00502   { 5, 16, 0, PPC_OPERAND_GPR },
00503 
00504   /* The RB field in an X, XO, M, or MDS form instruction.  */
00505 #define RB (44)
00506 #define RB_MASK (0x1f << 11)
00507   { 5, 11, 0, PPC_OPERAND_GPR },
00508 
00509   /* The RB field in an X form instruction when it must be the same as
00510      the RS field in the instruction.  This is used for extended
00511      mnemonics like mr.  */
00512 #define RBS (45)
00513   { 5, 1, extract_rbs, PPC_OPERAND_FAKE },
00514 
00515   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
00516      instruction or the RT field in a D, DS, X, XFX or XO form
00517      instruction.  */
00518 #define RS (46)
00519 #define RT (RS)
00520 #define RT_MASK (0x1f << 21)
00521   { 5, 21, 0, PPC_OPERAND_GPR },
00522 
00523   /* The SH field in an X or M form instruction.  */
00524 #define SH (47)
00525 #define SH_MASK (0x1f << 11)
00526   { 5, 11, 0, 0 },
00527 
00528   /* The SH field in an MD form instruction.  This is split.  */
00529 #define SH6 (48)
00530 #define SH6_MASK ((0x1f << 11) | (1 << 1))
00531   { 6, 1, extract_sh6, 0 },
00532 
00533   /* The SI field in a D form instruction.  */
00534 #define SI (49)
00535   { 16, 0, 0, PPC_OPERAND_SIGNED },
00536 
00537   /* The SI field in a D form instruction when we accept a wide range
00538      of positive values.  */
00539 #define SISIGNOPT (50)
00540   { 16, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
00541 
00542   /* The SPR field in an XFX form instruction.  This is flipped--the
00543      lower 5 bits are stored in the upper 5 and vice- versa.  */
00544 #define SPR (51)
00545 #define SPR_MASK (0x3ff << 11)
00546   { 10, 11, extract_spr, 0 },
00547 
00548   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
00549 #define SPRBAT (52)
00550 #define SPRBAT_MASK (0x3 << 17)
00551   { 2, 17, 0, 0 },
00552 
00553   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
00554 #define SPRG (53)
00555 #define SPRG_MASK (0x3 << 16)
00556   { 2, 16, 0, 0 },
00557 
00558   /* The SR field in an X form instruction.  */
00559 #define SR (54)
00560   { 4, 16, 0, 0 },
00561 
00562   /* The SV field in a POWER SC form instruction.  */
00563 #define SV (55)
00564   { 14, 2, 0, 0 },
00565 
00566   /* The TBR field in an XFX form instruction.  This is like the SPR
00567      field, but it is optional.  */
00568 #define TBR (56)
00569   { 10, 11, extract_tbr, PPC_OPERAND_OPTIONAL },
00570 
00571   /* The TO field in a D or X form instruction.  */
00572 #define TO (57)
00573 #define TO_MASK (0x1f << 21)
00574   { 5, 21, 0, 0 },
00575 
00576   /* The U field in an X form instruction.  */
00577 #define U (58)
00578   { 4, 12, 0, 0 },
00579 
00580   /* The UI field in a D form instruction.  */
00581 #define UI (59)
00582   { 16, 0, 0, 0 },
00583 };
00584 
00585 
00586 /* Macros used to form opcodes.  */
00587 
00588 /* The main opcode.  */
00589 #define OP(x) (((x) & 0x3f) << 26)
00590 #define OP_MASK OP (0x3f)
00591 
00592 /* The main opcode combined with a trap code in the TO field of a D
00593    form instruction.  Used for extended mnemonics for the trap
00594    instructions.  */
00595 #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
00596 #define OPTO_MASK (OP_MASK | TO_MASK)
00597 
00598 /* The main opcode combined with a comparison size bit in the L field
00599    of a D form or X form instruction.  Used for extended mnemonics for
00600    the comparison instructions.  */
00601 #define OPL(x,l) (OP (x) | (((l) & 1) << 21))
00602 #define OPL_MASK OPL (0x3f,1)
00603 
00604 /* An A form instruction.  */
00605 #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
00606 #define A_MASK A (0x3f, 0x1f, 1)
00607 
00608 /* An A_MASK with the FRB field fixed.  */
00609 #define AFRB_MASK (A_MASK | FRB_MASK)
00610 
00611 /* An A_MASK with the FRC field fixed.  */
00612 #define AFRC_MASK (A_MASK | FRC_MASK)
00613 
00614 /* An A_MASK with the FRA and FRC fields fixed.  */
00615 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
00616 
00617 /* A B form instruction.  */
00618 #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
00619 #define B_MASK B (0x3f, 1, 1)
00620 
00621 /* A B form instruction setting the BO field.  */
00622 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
00623 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
00624 
00625 /* A BBO_MASK with the y bit of the BO field removed.  This permits
00626    matching a conditional branch regardless of the setting of the y
00627    bit.  */
00628 #define Y_MASK (1 << 21)
00629 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
00630 
00631 /* A B form instruction setting the BO field and the condition bits of
00632    the BI field.  */
00633 #define BBOCB(op, bo, cb, aa, lk) (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
00634 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
00635 
00636 /* A BBOCB_MASK with the y bit of the BO field removed.  */
00637 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
00638 
00639 /* A BBOYCB_MASK in which the BI field is fixed.  */
00640 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
00641 
00642 /* The main opcode mask with the RA field clear.  */
00643 #define DRA_MASK (OP_MASK | RA_MASK)
00644 
00645 /* A DS form instruction.  */
00646 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
00647 #define DS_MASK DSO (0x3f, 3)
00648 
00649 /* An M form instruction.  */
00650 #define M(op, rc) (OP (op) | ((rc) & 1))
00651 #define M_MASK M (0x3f, 1)
00652 
00653 /* An M form instruction with the ME field specified.  */
00654 #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
00655 
00656 /* An M_MASK with the MB and ME fields fixed.  */
00657 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
00658 
00659 /* An M_MASK with the SH and ME fields fixed.  */
00660 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
00661 
00662 /* An MD form instruction.  */
00663 #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
00664 #define MD_MASK MD (0x3f, 0x7, 1)
00665 
00666 /* An MD_MASK with the MB field fixed.  */
00667 #define MDMB_MASK (MD_MASK | MB6_MASK)
00668 
00669 /* An MD_MASK with the SH field fixed.  */
00670 #define MDSH_MASK (MD_MASK | SH6_MASK)
00671 
00672 /* An MDS form instruction.  */
00673 #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
00674 #define MDS_MASK MDS (0x3f, 0xf, 1)
00675 
00676 /* An MDS_MASK with the MB field fixed.  */
00677 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
00678 
00679 /* An SC form instruction.  */
00680 #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
00681 #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
00682 
00683 /* An X form instruction.  */
00684 #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
00685 
00686 /* An X form instruction with the RC bit specified.  */
00687 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
00688 
00689 /* The mask for an X form instruction.  */
00690 #define X_MASK XRC (0x3f, 0x3ff, 1)
00691 
00692 /* An X_MASK with the RA field fixed.  */
00693 #define XRA_MASK (X_MASK | RA_MASK)
00694 
00695 /* An X_MASK with the RB field fixed.  */
00696 #define XRB_MASK (X_MASK | RB_MASK)
00697 
00698 /* An X_MASK with the RT field fixed.  */
00699 #define XRT_MASK (X_MASK | RT_MASK)
00700 
00701 /* An X_MASK with the RA and RB fields fixed.  */
00702 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
00703 
00704 /* An X_MASK with the RT and RA fields fixed.  */
00705 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
00706 
00707 /* An X form comparison instruction.  */
00708 #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
00709 
00710 /* The mask for an X form comparison instruction.  */
00711 #define XCMP_MASK (X_MASK | (1 << 22))
00712 
00713 /* The mask for an X form comparison instruction with the L field
00714    fixed.  */
00715 #define XCMPL_MASK (XCMP_MASK | (1 << 21))
00716 
00717 /* An X form trap instruction with the TO field specified.  */
00718 #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
00719 #define XTO_MASK (X_MASK | TO_MASK)
00720 
00721 /* An XFL form instruction.  */
00722 #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
00723 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
00724 
00725 /* An XL form instruction with the LK field set to 0.  */
00726 #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
00727 
00728 /* An XL form instruction which uses the LK field.  */
00729 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
00730 
00731 /* The mask for an XL form instruction.  */
00732 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
00733 
00734 /* An XL form instruction which explicitly sets the BO field.  */
00735 #define XLO(op, bo, xop, lk) (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
00736 #define XLO_MASK (XL_MASK | BO_MASK)
00737 
00738 /* An XL form instruction which explicitly sets the y bit of the BO
00739    field.  */
00740 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
00741 #define XLYLK_MASK (XL_MASK | Y_MASK)
00742 
00743 /* An XL form instruction which sets the BO field and the condition
00744    bits of the BI field.  */
00745 #define XLOCB(op, bo, cb, xop, lk) (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
00746 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
00747 
00748 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
00749 #define XLBB_MASK (XL_MASK | BB_MASK)
00750 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
00751 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
00752 
00753 /* An XL_MASK with the BO and BB fields fixed.  */
00754 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
00755 
00756 /* An XL_MASK with the BO, BI and BB fields fixed.  */
00757 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
00758 
00759 /* An XO form instruction.  */
00760 #define XO(op, xop, oe, rc) (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
00761 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
00762 
00763 /* An XO_MASK with the RB field fixed.  */
00764 #define XORB_MASK (XO_MASK | RB_MASK)
00765 
00766 /* An XS form instruction.  */
00767 #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
00768 #define XS_MASK XS (0x3f, 0x1ff, 1)
00769 
00770 /* A mask for the FXM version of an XFX form instruction.  */
00771 #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
00772 
00773 /* An XFX form instruction with the FXM field filled in.  */
00774 #define XFXM(op, xop, fxm) (X ((op), (xop)) | (((fxm) & 0xff) << 12))
00775 
00776 /* An XFX form instruction with the SPR field filled in.  */
00777 #define XSPR(op, xop, spr) (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
00778 #define XSPR_MASK (X_MASK | SPR_MASK)
00779 
00780 /* An XFX form instruction with the SPR field filled in except for the
00781    SPRBAT field.  */
00782 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
00783 
00784 /* An XFX form instruction with the SPR field filled in except for the
00785    SPRG field.  */
00786 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
00787 
00788 /* The BO encodings used in extended conditional branch mnemonics.  */
00789 #define BODNZF  (0x0)
00790 #define BODNZFP (0x1)
00791 #define BODZF   (0x2)
00792 #define BODZFP  (0x3)
00793 #define BOF     (0x4)
00794 #define BOFP    (0x5)
00795 #define BODNZT  (0x8)
00796 #define BODNZTP (0x9)
00797 #define BODZT   (0xa)
00798 #define BODZTP  (0xb)
00799 #define BOT     (0xc)
00800 #define BOTP    (0xd)
00801 #define BODNZ   (0x10)
00802 #define BODNZP  (0x11)
00803 #define BODZ    (0x12)
00804 #define BODZP   (0x13)
00805 #define BOU     (0x14)
00806 
00807 /* The BI condition bit encodings used in extended conditional branch
00808    mnemonics.  */
00809 #define CBLT    (0)
00810 #define CBGT    (1)
00811 #define CBEQ    (2)
00812 #define CBSO    (3)
00813 
00814 /* The TO encodings used in extended trap mnemonics.  */
00815 #define TOLGT   (0x1)
00816 #define TOLLT   (0x2)
00817 #define TOEQ    (0x4)
00818 #define TOLGE   (0x5)
00819 #define TOLNL   (0x5)
00820 #define TOLLE   (0x6)
00821 #define TOLNG   (0x6)
00822 #define TOGT    (0x8)
00823 #define TOGE    (0xc)
00824 #define TONL    (0xc)
00825 #define TOLT    (0x10)
00826 #define TOLE    (0x14)
00827 #define TONG    (0x14)
00828 #define TONE    (0x18)
00829 #define TOU     (0x1f)
00830 
00831 /* Smaller names for the flags so each entry in the opcodes table will
00832    fit on a single line.  */
00833 #undef PPC
00834 #define PPC PPC_OPCODE_PPC
00835 #define POWER PPC_OPCODE_POWER
00836 #define POWER2 PPC_OPCODE_POWER2
00837 #define B32 PPC_OPCODE_32
00838 #define B64 PPC_OPCODE_64
00839 #define M601 PPC_OPCODE_601
00840 
00841 /* The opcode table.
00842 
00843    The format of the opcode table is:
00844 
00845    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
00846 
00847    NAME is the name of the instruction.
00848    OPCODE is the instruction opcode.
00849    MASK is the opcode mask; this is used to tell the disassembler
00850      which bits in the actual opcode must match OPCODE.
00851    FLAGS are flags indicated what processors support the instruction.
00852    OPERANDS is the list of operands.
00853 
00854    The disassembler reads the table in order and prints the first
00855    instruction which matches, so this table is sorted to put more
00856    specific instructions before more general instructions.  It is also
00857    sorted by major opcode.  */
00858 
00859 const struct powerpc_opcode powerpc_opcodes[] = {
00860 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC|B64,        { RA, SI } },
00861 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC|B64,        { RA, SI } },
00862 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC|B64,        { RA, SI } },
00863 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC|B64,        { RA, SI } },
00864 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC|B64,        { RA, SI } },
00865 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC|B64,        { RA, SI } },
00866 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC|B64,        { RA, SI } },
00867 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC|B64,        { RA, SI } },
00868 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC|B64,        { RA, SI } },
00869 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC|B64,        { RA, SI } },
00870 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC|B64,        { RA, SI } },
00871 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC|B64,        { RA, SI } },
00872 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC|B64,        { RA, SI } },
00873 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC|B64,        { RA, SI } },
00874 { "tdi",     OP(2),     OP_MASK,        PPC|B64,        { TO, RA, SI } },
00875 
00876 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPC,            { RA, SI } },
00877 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  POWER,  { RA, SI } },
00878 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPC,            { RA, SI } },
00879 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  POWER,  { RA, SI } },
00880 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPC,            { RA, SI } },
00881 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   POWER,  { RA, SI } },
00882 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPC,            { RA, SI } },
00883 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  POWER,  { RA, SI } },
00884 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPC,            { RA, SI } },
00885 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  POWER,  { RA, SI } },
00886 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPC,            { RA, SI } },
00887 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  POWER,  { RA, SI } },
00888 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPC,            { RA, SI } },
00889 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  POWER,  { RA, SI } },
00890 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPC,            { RA, SI } },
00891 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   POWER,  { RA, SI } },
00892 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPC,            { RA, SI } },
00893 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   POWER,  { RA, SI } },
00894 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPC,            { RA, SI } },
00895 { "tnli",    OPTO(3,TONL), OPTO_MASK,   POWER,  { RA, SI } },
00896 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPC,            { RA, SI } },
00897 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   POWER,  { RA, SI } },
00898 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPC,            { RA, SI } },
00899 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   POWER,  { RA, SI } },
00900 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPC,            { RA, SI } },
00901 { "tngi",    OPTO(3,TONG), OPTO_MASK,   POWER,  { RA, SI } },
00902 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPC,            { RA, SI } },
00903 { "tnei",    OPTO(3,TONE), OPTO_MASK,   POWER,  { RA, SI } },
00904 { "twi",     OP(3),     OP_MASK,        PPC,            { TO, RA, SI } },
00905 { "ti",      OP(3),     OP_MASK,        POWER,  { TO, RA, SI } },
00906 
00907 { "mulli",   OP(7),     OP_MASK,        PPC,            { RT, RA, SI } },
00908 { "muli",    OP(7),     OP_MASK,        POWER,  { RT, RA, SI } },
00909 
00910 { "subfic",  OP(8),     OP_MASK,        PPC,            { RT, RA, SI } },
00911 { "sfi",     OP(8),     OP_MASK,        POWER,  { RT, RA, SI } },
00912 
00913 { "dozi",    OP(9),     OP_MASK,        POWER|M601,     { RT, RA, SI } },
00914 
00915 { "cmplwi",  OPL(10,0), OPL_MASK,       PPC,            { OBF, RA, UI } },
00916 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC|B64,        { OBF, RA, UI } },
00917 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
00918 { "cmpli",   OP(10),    OP_MASK,        POWER,  { BF, RA, UI } },
00919 
00920 { "cmpwi",   OPL(11,0), OPL_MASK,       PPC,            { OBF, RA, SI } },
00921 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC|B64,        { OBF, RA, SI } },
00922 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
00923 { "cmpi",    OP(11),    OP_MASK,        POWER,  { BF, RA, SI } },
00924 
00925 { "addic",   OP(12),    OP_MASK,        PPC,            { RT, RA, SI } },
00926 { "ai",      OP(12),    OP_MASK,        POWER,  { RT, RA, SI } },
00927 { "subic",   OP(12),    OP_MASK,        PPC,            { RT, RA, NSI } },
00928 
00929 { "addic.",  OP(13),    OP_MASK,        PPC,            { RT, RA, SI } },
00930 { "ai.",     OP(13),    OP_MASK,        POWER,  { RT, RA, SI } },
00931 { "subic.",  OP(13),    OP_MASK,        PPC,            { RT, RA, NSI } },
00932 
00933 { "li",      OP(14),    DRA_MASK,       PPC,            { RT, SI } },
00934 { "lil",     OP(14),    DRA_MASK,       POWER,  { RT, SI } },
00935 { "addi",    OP(14),    OP_MASK,        PPC,            { RT, RA, SI } },
00936 { "cal",     OP(14),    OP_MASK,        POWER,  { RT, D, RA } },
00937 { "subi",    OP(14),    OP_MASK,        PPC,            { RT, RA, NSI } },
00938 { "la",      OP(14),    OP_MASK,        PPC,            { RT, D, RA } },
00939 
00940 { "lis",     OP(15),    DRA_MASK,       PPC,            { RT, SISIGNOPT } },
00941 { "liu",     OP(15),    DRA_MASK,       POWER,  { RT, SISIGNOPT } },
00942 { "addis",   OP(15),    OP_MASK,        PPC,            { RT,RA,SISIGNOPT } },
00943 { "cau",     OP(15),    OP_MASK,        POWER,  { RT,RA,SISIGNOPT } },
00944 { "subis",   OP(15),    OP_MASK,        PPC,            { RT, RA, NSI } },
00945 
00946 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDM } },
00947 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDP } },
00948 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BD } },
00949 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER,     { BD } },
00950 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDM } },
00951 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDP } },
00952 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BD } },
00953 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER,     { BD } },
00954 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDMA } },
00955 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDPA } },
00956 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDA } },
00957 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER,     { BDA } },
00958 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDMA } },
00959 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDPA } },
00960 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDA } },
00961 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER,     { BDA } },
00962 { "bdz-",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,        { BDM } },
00963 { "bdz+",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,        { BDP } },
00964 { "bdz",     BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER,  { BD } },
00965 { "bdzl-",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,        { BDM } },
00966 { "bdzl+",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,        { BDP } },
00967 { "bdzl",    BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER,  { BD } },
00968 { "bdza-",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,        { BDMA } },
00969 { "bdza+",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,        { BDPA } },
00970 { "bdza",    BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER,  { BDA } },
00971 { "bdzla-",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,        { BDMA } },
00972 { "bdzla+",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,        { BDPA } },
00973 { "bdzla",   BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER,  { BDA } },
00974 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
00975 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
00976 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
00977 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
00978 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
00979 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
00980 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
00981 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
00982 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
00983 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
00984 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
00985 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
00986 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
00987 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
00988 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
00989 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
00990 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
00991 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
00992 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
00993 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
00994 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
00995 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
00996 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
00997 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
00998 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
00999 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01000 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01001 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01002 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01003 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01004 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01005 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01006 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01007 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01008 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01009 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01010 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01011 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01012 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01013 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01014 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01015 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01016 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01017 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01018 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01019 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01020 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01021 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01022 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01023 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01024 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BD } },
01025 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01026 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01027 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BD } },
01028 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01029 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01030 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDA } },
01031 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01032 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01033 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDA } },
01034 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01035 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01036 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01037 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01038 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01039 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01040 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01041 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01042 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01043 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01044 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01045 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01046 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01047 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01048 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01049 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01050 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01051 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01052 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01053 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01054 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01055 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01056 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01057 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01058 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01059 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01060 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01061 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01062 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01063 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01064 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01065 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01066 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01067 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01068 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01069 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01070 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01071 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01072 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01073 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01074 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01075 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01076 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01077 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01078 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01079 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01080 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01081 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01082 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01083 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01084 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01085 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01086 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01087 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01088 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01089 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01090 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01091 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01092 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01093 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01094 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01095 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01096 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01097 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01098 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01099 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
01100 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01101 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01102 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01103 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01104 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01105 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
01106 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
01107 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
01108 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BD } },
01109 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
01110 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
01111 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BD } },
01112 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
01113 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
01114 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDA } },
01115 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
01116 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
01117 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDA } },
01118 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDM } },
01119 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDP } },
01120 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BD } },
01121 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDM } },
01122 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDP } },
01123 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BD } },
01124 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
01125 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
01126 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDA } },
01127 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
01128 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
01129 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDA } },
01130 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDM } },
01131 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDP } },
01132 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BD } },
01133 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDM } },
01134 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDP } },
01135 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BD } },
01136 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
01137 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
01138 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDA } },
01139 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
01140 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
01141 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDA } },
01142 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDM } },
01143 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDP } },
01144 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BD } },
01145 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, POWER,         { BI, BD } },
01146 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDM } },
01147 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDP } },
01148 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BD } },
01149 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, POWER,         { BI, BD } },
01150 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
01151 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
01152 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDA } },
01153 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, POWER,         { BI, BDA } },
01154 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
01155 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
01156 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDA } },
01157 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, POWER,         { BI, BDA } },
01158 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDM } },
01159 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDP } },
01160 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BD } },
01161 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, POWER,         { BI, BD } },
01162 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDM } },
01163 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDP } },
01164 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BD } },
01165 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, POWER,         { BI, BD } },
01166 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
01167 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
01168 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDA } },
01169 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, POWER,         { BI, BDA } },
01170 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
01171 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
01172 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDA } },
01173 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, POWER,         { BI, BDA } },
01174 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDM } },
01175 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDP } },
01176 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BD } },
01177 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDM } },
01178 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDP } },
01179 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BD } },
01180 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
01181 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
01182 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDA } },
01183 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
01184 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
01185 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDA } },
01186 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDM } },
01187 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDP } },
01188 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BD } },
01189 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDM } },
01190 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDP } },
01191 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BD } },
01192 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
01193 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
01194 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDA } },
01195 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
01196 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
01197 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDA } },
01198 { "bc-",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDM } },
01199 { "bc+",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDP } },
01200 { "bc",      B(16,0,0), B_MASK,         PPC|POWER,      { BO, BI, BD } },
01201 { "bcl-",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDM } },
01202 { "bcl+",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDP } },
01203 { "bcl",     B(16,0,1), B_MASK,         PPC|POWER,      { BO, BI, BD } },
01204 { "bca-",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDMA } },
01205 { "bca+",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDPA } },
01206 { "bca",     B(16,1,0), B_MASK,         PPC|POWER,      { BO, BI, BDA } },
01207 { "bcla-",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDMA } },
01208 { "bcla+",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDPA } },
01209 { "bcla",    B(16,1,1), B_MASK,         PPC|POWER,      { BO, BI, BDA } },
01210 
01211 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
01212 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
01213 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
01214 { "svca",    SC(17,1,0), SC_MASK,       POWER,          { SV } },
01215 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
01216 
01217 { "b",       B(18,0,0), B_MASK,         PPC|POWER,      { LI } },
01218 { "bl",      B(18,0,1), B_MASK,         PPC|POWER,      { LI } },
01219 { "ba",      B(18,1,0), B_MASK,         PPC|POWER,      { LIA } },
01220 { "bla",     B(18,1,1), B_MASK,         PPC|POWER,      { LIA } },
01221 
01222 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
01223 
01224 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC,      { 0 } },
01225 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER,    { 0 } },
01226 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC,      { 0 } },
01227 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER,    { 0 } },
01228 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
01229 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
01230 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC,   { 0 } },
01231 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
01232 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
01233 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC,   { 0 } },
01234 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,     { 0 } },
01235 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,     { 0 } },
01236 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
01237 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,     { 0 } },
01238 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,     { 0 } },
01239 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
01240 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01241 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01242 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01243 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01244 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01245 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01246 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01247 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01248 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01249 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01250 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01251 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01252 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01253 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01254 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01255 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01256 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01257 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01258 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01259 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
01260 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01261 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01262 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01263 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
01264 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01265 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01266 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01267 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
01268 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01269 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01270 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01271 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
01272 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01273 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01274 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01275 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01276 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01277 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01278 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01279 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01280 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01281 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01282 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01283 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01284 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01285 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01286 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01287 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01288 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01289 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01290 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01291 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01292 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01293 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01294 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01295 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01296 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01297 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01298 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01299 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01300 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01301 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01302 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01303 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01304 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
01305 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
01306 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01307 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01308 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
01309 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
01310 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01311 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01312 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
01313 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
01314 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01315 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01316 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
01317 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
01318 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01319 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01320 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01321 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
01322 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01323 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01324 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01325 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
01326 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01327 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01328 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
01329 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01330 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01331 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
01332 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPC,        { BI } },
01333 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPC,        { BI } },
01334 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPC,       { BI } },
01335 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, POWER,      { BI } },
01336 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPC,        { BI } },
01337 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPC,        { BI } },
01338 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPC,       { BI } },
01339 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, POWER,      { BI } },
01340 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPC,        { BI } },
01341 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPC,        { BI } },
01342 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPC,       { BI } },
01343 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, POWER,      { BI } },
01344 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPC,        { BI } },
01345 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPC,        { BI } },
01346 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPC,       { BI } },
01347 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, POWER,      { BI } },
01348 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,     { BI } },
01349 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,     { BI } },
01350 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC,    { BI } },
01351 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,     { BI } },
01352 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,    { BI } },
01353 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC,   { BI } },
01354 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,     { BI } },
01355 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,     { BI } },
01356 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC,    { BI } },
01357 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,     { BI } },
01358 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,    { BI } },
01359 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC,   { BI } },
01360 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,      { BI } },
01361 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,      { BI } },
01362 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC,     { BI } },
01363 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,      { BI } },
01364 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,      { BI } },
01365 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC,     { BI } },
01366 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,      { BI } },
01367 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,      { BI } },
01368 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC,     { BI } },
01369 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,      { BI } },
01370 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,      { BI } },
01371 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC,     { BI } },
01372 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPC,            { BO, BI } },
01373 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPC,            { BO, BI } },
01374 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPC,         { BOE, BI } },
01375 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPC,         { BOE, BI } },
01376 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPC,         { BOE, BI } },
01377 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPC,         { BOE, BI } },
01378 { "bcr",     XLLK(19,16,0), XLBB_MASK,  POWER,          { BO, BI } },
01379 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  POWER,          { BO, BI } },
01380 
01381 { "crnot",   XL(19,33), XL_MASK,        PPC,            { BT, BA, BBA } },
01382 { "crnor",   XL(19,33), XL_MASK,        PPC|POWER,      { BT, BA, BB } },
01383 
01384 { "rfi",     XL(19,50), 0xffffffff,     PPC|POWER,      { 0 } },
01385 { "rfci",    XL(19,51), 0xffffffff,     PPC,            { 0 } },
01386 
01387 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
01388 
01389 { "crandc",  XL(19,129), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01390 
01391 { "isync",   XL(19,150), 0xffffffff,    PPC,            { 0 } },
01392 { "ics",     XL(19,150), 0xffffffff,    POWER,          { 0 } },
01393 
01394 { "crclr",   XL(19,193), XL_MASK,       PPC,            { BT, BAT, BBA } },
01395 { "crxor",   XL(19,193), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01396 
01397 { "crnand",  XL(19,225), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01398 
01399 { "crand",   XL(19,257), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01400 
01401 { "crset",   XL(19,289), XL_MASK,       PPC,            { BT, BAT, BBA } },
01402 { "creqv",   XL(19,289), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01403 
01404 { "crorc",   XL(19,417), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01405 
01406 { "crmove",  XL(19,449), XL_MASK,       PPC,            { BT, BA, BBA } },
01407 { "cror",    XL(19,449), XL_MASK,       PPC|POWER,      { BT, BA, BB } },
01408 
01409 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
01410 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
01411 { "bltctr",  XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01412 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01413 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01414 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01415 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01416 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01417 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01418 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01419 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01420 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01421 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01422 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01423 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01424 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01425 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01426 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01427 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01428 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01429 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01430 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01431 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01432 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01433 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01434 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01435 { "bunctr",  XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01436 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01437 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01438 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01439 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01440 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01441 { "bgectr",  XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01442 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01443 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01444 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01445 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01446 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01447 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01448 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01449 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01450 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01451 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01452 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01453 { "blectr",  XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01454 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01455 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01456 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01457 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01458 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01459 { "bngctr",  XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01460 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01461 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
01462 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01463 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01464 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
01465 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01466 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01467 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
01468 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01469 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01470 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
01471 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01472 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01473 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01474 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01475 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01476 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01477 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01478 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01479 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
01480 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01481 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01482 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
01483 { "btctr",   XLO(19,BOT,528,0), XLBOBB_MASK, PPC,       { BI } },
01484 { "btctr-",  XLO(19,BOT,528,0), XLBOBB_MASK, PPC,       { BI } },
01485 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPC,      { BI } },
01486 { "btctrl",  XLO(19,BOT,528,1), XLBOBB_MASK, PPC,       { BI } },
01487 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC,       { BI } },
01488 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC,      { BI } },
01489 { "bfctr",   XLO(19,BOF,528,0), XLBOBB_MASK, PPC,       { BI } },
01490 { "bfctr-",  XLO(19,BOF,528,0), XLBOBB_MASK, PPC,       { BI } },
01491 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPC,      { BI } },
01492 { "bfctrl",  XLO(19,BOF,528,1), XLBOBB_MASK, PPC,       { BI } },
01493 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC,       { BI } },
01494 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC,      { BI } },
01495 { "bcctr",   XLLK(19,528,0), XLYBB_MASK, PPC,           { BO, BI } },
01496 { "bcctr-",  XLYLK(19,528,0,0), XLYBB_MASK, PPC,        { BOE, BI } },
01497 { "bcctr+",  XLYLK(19,528,1,0), XLYBB_MASK, PPC,        { BOE, BI } },
01498 { "bcctrl",  XLLK(19,528,1), XLYBB_MASK, PPC,           { BO, BI } },
01499 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC,        { BOE, BI } },
01500 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC,        { BOE, BI } },
01501 { "bcc",     XLLK(19,528,0), XLBB_MASK, POWER,          { BO, BI } },
01502 { "bccl",    XLLK(19,528,1), XLBB_MASK, POWER,          { BO, BI } },
01503 
01504 { "rlwimi",  M(20,0),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
01505 { "rlimi",   M(20,0),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
01506 
01507 { "rlwimi.", M(20,1),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
01508 { "rlimi.",  M(20,1),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
01509 
01510 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPC,            { RA, RS, SH } },
01511 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPC,            { RA, RS, MB } },
01512 { "rlwinm",  M(21,0),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
01513 { "rlinm",   M(21,0),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
01514 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPC,            { RA,RS,SH } },
01515 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPC,            { RA, RS, MB } },
01516 { "rlwinm.", M(21,1),   M_MASK,         PPC,            { RA,RS,SH,MBE,ME } },
01517 { "rlinm.",  M(21,1),   M_MASK,         POWER,          { RA,RS,SH,MBE,ME } },
01518 
01519 { "rlmi",    M(22,0),   M_MASK,         POWER|M601,     { RA,RS,RB,MBE,ME } },
01520 { "rlmi.",   M(22,1),   M_MASK,         POWER|M601,     { RA,RS,RB,MBE,ME } },
01521 
01522 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPC,            { RA, RS, RB } },
01523 { "rlwnm",   M(23,0),   M_MASK,         PPC,            { RA,RS,RB,MBE,ME } },
01524 { "rlnm",    M(23,0),   M_MASK,         POWER,          { RA,RS,RB,MBE,ME } },
01525 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPC,            { RA, RS, RB } },
01526 { "rlwnm.",  M(23,1),   M_MASK,         PPC,            { RA,RS,RB,MBE,ME } },
01527 { "rlnm.",   M(23,1),   M_MASK,         POWER,          { RA,RS,RB,MBE,ME } },
01528 
01529 { "nop",     OP(24),    0xffffffff,     PPC,            { 0 } },
01530 { "ori",     OP(24),    OP_MASK,        PPC,            { RA, RS, UI } },
01531 { "oril",    OP(24),    OP_MASK,        POWER,          { RA, RS, UI } },
01532 
01533 { "oris",    OP(25),    OP_MASK,        PPC,            { RA, RS, UI } },
01534 { "oriu",    OP(25),    OP_MASK,        POWER,          { RA, RS, UI } },
01535 
01536 { "xori",    OP(26),    OP_MASK,        PPC,            { RA, RS, UI } },
01537 { "xoril",   OP(26),    OP_MASK,        POWER,          { RA, RS, UI } },
01538 
01539 { "xoris",   OP(27),    OP_MASK,        PPC,            { RA, RS, UI } },
01540 { "xoriu",   OP(27),    OP_MASK,        POWER,          { RA, RS, UI } },
01541 
01542 { "andi.",   OP(28),    OP_MASK,        PPC,            { RA, RS, UI } },
01543 { "andil.",  OP(28),    OP_MASK,        POWER,          { RA, RS, UI } },
01544 
01545 { "andis.",  OP(29),    OP_MASK,        PPC,            { RA, RS, UI } },
01546 { "andiu.",  OP(29),    OP_MASK,        POWER,          { RA, RS, UI } },
01547 
01548 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC|B64,        { RA, RS, SH6 } },
01549 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC|B64,        { RA, RS, MB6 } },
01550 { "rldicl",  MD(30,0,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01551 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC|B64,        { RA, RS, SH6 } },
01552 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC|B64,        { RA, RS, MB6 } },
01553 { "rldicl.", MD(30,0,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01554 
01555 { "rldicr",  MD(30,1,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, ME6 } },
01556 { "rldicr.", MD(30,1,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, ME6 } },
01557 
01558 { "rldic",   MD(30,2,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01559 { "rldic.",  MD(30,2,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01560 
01561 { "rldimi",  MD(30,3,0), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01562 { "rldimi.", MD(30,3,1), MD_MASK,       PPC|B64,        { RA, RS, SH6, MB6 } },
01563 
01564 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC|B64,        { RA, RS, RB } },
01565 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC|B64,        { RA, RS, RB, MB6 } },
01566 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC|B64,        { RA, RS, RB } },
01567 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC|B64,        { RA, RS, RB, MB6 } },
01568 
01569 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC|B64,        { RA, RS, RB, ME6 } },
01570 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC|B64,        { RA, RS, RB, ME6 } },
01571 
01572 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPC,            { OBF, RA, RB } },
01573 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC|B64,        { OBF, RA, RB } },
01574 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
01575 { "cmp",     X(31,0),   XCMPL_MASK,     POWER,          { BF, RA, RB } },
01576 
01577 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPC,            { RA, RB } },
01578 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, POWER,          { RA, RB } },
01579 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPC,            { RA, RB } },
01580 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, POWER,          { RA, RB } },
01581 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPC,            { RA, RB } },
01582 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  POWER,          { RA, RB } },
01583 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPC,            { RA, RB } },
01584 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, POWER,          { RA, RB } },
01585 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPC,            { RA, RB } },
01586 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, POWER,          { RA, RB } },
01587 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPC,            { RA, RB } },
01588 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, POWER,          { RA, RB } },
01589 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPC,            { RA, RB } },
01590 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, POWER,          { RA, RB } },
01591 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPC,            { RA, RB } },
01592 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  POWER,          { RA, RB } },
01593 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPC,            { RA, RB } },
01594 { "tge",     XTO(31,4,TOGE), XTO_MASK,  POWER,          { RA, RB } },
01595 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPC,            { RA, RB } },
01596 { "tnl",     XTO(31,4,TONL), XTO_MASK,  POWER,          { RA, RB } },
01597 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPC,            { RA, RB } },
01598 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  POWER,          { RA, RB } },
01599 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPC,            { RA, RB } },
01600 { "tle",     XTO(31,4,TOLE), XTO_MASK,  POWER,          { RA, RB } },
01601 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPC,            { RA, RB } },
01602 { "tng",     XTO(31,4,TONG), XTO_MASK,  POWER,          { RA, RB } },
01603 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPC,            { RA, RB } },
01604 { "tne",     XTO(31,4,TONE), XTO_MASK,  POWER,          { RA, RB } },
01605 { "trap",    XTO(31,4,TOU), 0xffffffff, PPC,            { 0 } },
01606 { "tw",      X(31,4),   X_MASK,         PPC,            { TO, RA, RB } },
01607 { "t",       X(31,4),   X_MASK,         POWER,          { TO, RA, RB } },
01608 
01609 { "subfc",   XO(31,8,0,0), XO_MASK,     PPC,            { RT, RA, RB } },
01610 { "sf",      XO(31,8,0,0), XO_MASK,     POWER,          { RT, RA, RB } },
01611 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
01612 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPC,            { RT, RA, RB } },
01613 { "sf.",     XO(31,8,0,1), XO_MASK,     POWER,          { RT, RA, RB } },
01614 { "subc.",   XO(31,8,0,1), XO_MASK,     PPC,            { RT, RB, RA } },
01615 { "subfco",  XO(31,8,1,0), XO_MASK,     PPC,            { RT, RA, RB } },
01616 { "sfo",     XO(31,8,1,0), XO_MASK,     POWER,          { RT, RA, RB } },
01617 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
01618 { "subfco.", XO(31,8,1,1), XO_MASK,     PPC,            { RT, RA, RB } },
01619 { "sfo.",    XO(31,8,1,1), XO_MASK,     POWER,          { RT, RA, RB } },
01620 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
01621 
01622 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC|B64,        { RT, RA, RB } },
01623 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC|B64,        { RT, RA, RB } },
01624 
01625 { "addc",    XO(31,10,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
01626 { "a",       XO(31,10,0,0), XO_MASK,    POWER,          { RT, RA, RB } },
01627 { "addc.",   XO(31,10,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
01628 { "a.",      XO(31,10,0,1), XO_MASK,    POWER,          { RT, RA, RB } },
01629 { "addco",   XO(31,10,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
01630 { "ao",      XO(31,10,1,0), XO_MASK,    POWER,          { RT, RA, RB } },
01631 { "addco.",  XO(31,10,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
01632 { "ao.",     XO(31,10,1,1), XO_MASK,    POWER,          { RT, RA, RB } },
01633 
01634 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
01635 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
01636 
01637 { "mfcr",    X(31,19),  XRARB_MASK,     POWER|PPC,      { RT } },
01638 
01639 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
01640 
01641 { "ldx",     X(31,21),  X_MASK,         PPC|B64,        { RT, RA, RB } },
01642 
01643 { "lwzx",    X(31,23),  X_MASK,         PPC,            { RT, RA, RB } },
01644 { "lx",      X(31,23),  X_MASK,         POWER,          { RT, RA, RB } },
01645 
01646 { "slw",     XRC(31,24,0), X_MASK,      PPC,            { RA, RS, RB } },
01647 { "sl",      XRC(31,24,0), X_MASK,      POWER,          { RA, RS, RB } },
01648 { "slw.",    XRC(31,24,1), X_MASK,      PPC,            { RA, RS, RB } },
01649 { "sl.",     XRC(31,24,1), X_MASK,      POWER,          { RA, RS, RB } },
01650 
01651 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPC,            { RA, RS } },
01652 { "cntlz",   XRC(31,26,0), XRB_MASK,    POWER,          { RA, RS } },
01653 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPC,            { RA, RS } },
01654 { "cntlz.",  XRC(31,26,1), XRB_MASK,    POWER,          { RA, RS } },
01655 
01656 { "sld",     XRC(31,27,0), X_MASK,      PPC|B64,        { RA, RS, RB } },
01657 { "sld.",    XRC(31,27,1), X_MASK,      PPC|B64,        { RA, RS, RB } },
01658 
01659 { "and",     XRC(31,28,0), X_MASK,      PPC|POWER,      { RA, RS, RB } },
01660 { "and.",    XRC(31,28,1), X_MASK,      PPC|POWER,      { RA, RS, RB } },
01661 
01662 { "maskg",   XRC(31,29,0), X_MASK,      POWER|M601,     { RA, RS, RB } },
01663 { "maskg.",  XRC(31,29,1), X_MASK,      POWER|M601,     { RA, RS, RB } },
01664 
01665 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPC,           { OBF, RA, RB } },
01666 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC|B64,       { OBF, RA, RB } },
01667 { "cmpl",    X(31,32),  XCMP_MASK,      PPC,            { BF, L, RA, RB } },
01668 { "cmpl",    X(31,32),  XCMPL_MASK,     POWER,          { BF, RA, RB } },
01669 
01670 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
01671 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
01672 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
01673 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
01674 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
01675 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
01676 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
01677 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
01678 
01679 { "ldux",    X(31,53),  X_MASK,         PPC|B64,        { RT, RAL, RB } },
01680 
01681 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
01682 
01683 { "lwzux",   X(31,55),  X_MASK,         PPC,            { RT, RAL, RB } },
01684 { "lux",     X(31,55),  X_MASK,         POWER,          { RT, RA, RB } },
01685 
01686 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC|B64,        { RA, RS } },
01687 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC|B64,        { RA, RS } },
01688 
01689 { "andc",    XRC(31,60,0), X_MASK,      PPC|POWER,      { RA, RS, RB } },
01690 { "andc.",   XRC(31,60,1), X_MASK,      PPC|POWER,      { RA, RS, RB } },
01691 
01692 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC|B64,       { RA, RB } },
01693 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC|B64,       { RA, RB } },
01694 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK, PPC|B64,        { RA, RB } },
01695 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC|B64,       { RA, RB } },
01696 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC|B64,       { RA, RB } },
01697 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC|B64,       { RA, RB } },
01698 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC|B64,       { RA, RB } },
01699 { "tdgt",    XTO(31,68,TOGT), XTO_MASK, PPC|B64,        { RA, RB } },
01700 { "tdge",    XTO(31,68,TOGE), XTO_MASK, PPC|B64,        { RA, RB } },
01701 { "tdnl",    XTO(31,68,TONL), XTO_MASK, PPC|B64,        { RA, RB } },
01702 { "tdlt",    XTO(31,68,TOLT), XTO_MASK, PPC|B64,        { RA, RB } },
01703 { "tdle",    XTO(31,68,TOLE), XTO_MASK, PPC|B64,        { RA, RB } },
01704 { "tdng",    XTO(31,68,TONG), XTO_MASK, PPC|B64,        { RA, RB } },
01705 { "tdne",    XTO(31,68,TONE), XTO_MASK, PPC|B64,        { RA, RB } },
01706 { "td",      X(31,68),  X_MASK,         PPC|B64,        { TO, RA, RB } },
01707 
01708 { "mulhd",   XO(31,73,0,0), XO_MASK,    PPC|B64,        { RT, RA, RB } },
01709 { "mulhd.",  XO(31,73,0,1), XO_MASK,    PPC|B64,        { RT, RA, RB } },
01710 
01711 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
01712 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
01713 
01714 { "mfmsr",   X(31,83),  XRARB_MASK,     PPC|POWER,      { RT } },
01715 
01716 { "ldarx",   X(31,84),  X_MASK,         PPC|B64,        { RT, RA, RB } },
01717 
01718 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
01719 
01720 { "lbzx",    X(31,87),  X_MASK,         PPC|POWER,      { RT, RA, RB } },
01721 
01722 { "neg",     XO(31,104,0,0), XORB_MASK, PPC|POWER,      { RT, RA } },
01723 { "neg.",    XO(31,104,0,1), XORB_MASK, PPC|POWER,      { RT, RA } },
01724 { "nego",    XO(31,104,1,0), XORB_MASK, PPC|POWER,      { RT, RA } },
01725 { "nego.",   XO(31,104,1,1), XORB_MASK, PPC|POWER,      { RT, RA } },
01726 
01727 { "mul",     XO(31,107,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01728 { "mul.",    XO(31,107,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01729 { "mulo",    XO(31,107,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01730 { "mulo.",   XO(31,107,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01731 
01732 { "clf",     X(31,118), XRB_MASK,       POWER,          { RT, RA } },
01733 
01734 { "lbzux",   X(31,119), X_MASK,         PPC|POWER,      { RT, RAL, RB } },
01735 
01736 { "not",     XRC(31,124,0), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
01737 { "nor",     XRC(31,124,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01738 { "not.",    XRC(31,124,1), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
01739 { "nor.",    XRC(31,124,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01740 
01741 { "subfe",   XO(31,136,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
01742 { "sfe",     XO(31,136,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
01743 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
01744 { "sfe.",    XO(31,136,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
01745 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
01746 { "sfeo",    XO(31,136,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
01747 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
01748 { "sfeo.",   XO(31,136,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
01749 
01750 { "adde",    XO(31,138,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
01751 { "ae",      XO(31,138,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
01752 { "adde.",   XO(31,138,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
01753 { "ae.",     XO(31,138,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
01754 { "addeo",   XO(31,138,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
01755 { "aeo",     XO(31,138,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
01756 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
01757 { "aeo.",    XO(31,138,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
01758 
01759 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
01760 { "mtcrf",   X(31,144), XFXFXM_MASK,    PPC|POWER,      { FXM, RS } },
01761 
01762 { "mtmsr",   X(31,146), XRARB_MASK,     PPC|POWER,      { RS } },
01763 { "mtmsrd",  X(31,178), XRARB_MASK,     PPC|POWER,      { RS } },
01764 
01765 { "stdx",    X(31,149), X_MASK,         PPC|B64,        { RS, RA, RB } },
01766 
01767 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
01768 
01769 { "stwx",    X(31,151), X_MASK,         PPC,            { RS, RA, RB } },
01770 { "stx",     X(31,151), X_MASK,         POWER,          { RS, RA, RB } },
01771 
01772 { "slq",     XRC(31,152,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
01773 { "slq.",    XRC(31,152,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
01774 
01775 { "sle",     XRC(31,153,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
01776 { "sle.",    XRC(31,153,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
01777 
01778 { "stdux",   X(31,181), X_MASK,         PPC|B64,        { RS, RAS, RB } },
01779 
01780 { "stwux",   X(31,183), X_MASK,         PPC,            { RS, RAS, RB } },
01781 { "stux",    X(31,183), X_MASK,         POWER,          { RS, RA, RB } },
01782 
01783 { "sliq",    XRC(31,184,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
01784 { "sliq.",   XRC(31,184,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
01785 
01786 { "subfze",  XO(31,200,0,0), XORB_MASK, PPC,            { RT, RA } },
01787 { "sfze",    XO(31,200,0,0), XORB_MASK, POWER,          { RT, RA } },
01788 { "subfze.", XO(31,200,0,1), XORB_MASK, PPC,            { RT, RA } },
01789 { "sfze.",   XO(31,200,0,1), XORB_MASK, POWER,          { RT, RA } },
01790 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC,            { RT, RA } },
01791 { "sfzeo",   XO(31,200,1,0), XORB_MASK, POWER,          { RT, RA } },
01792 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC,            { RT, RA } },
01793 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, POWER,          { RT, RA } },
01794 
01795 { "addze",   XO(31,202,0,0), XORB_MASK, PPC,            { RT, RA } },
01796 { "aze",     XO(31,202,0,0), XORB_MASK, POWER,          { RT, RA } },
01797 { "addze.",  XO(31,202,0,1), XORB_MASK, PPC,            { RT, RA } },
01798 { "aze.",    XO(31,202,0,1), XORB_MASK, POWER,          { RT, RA } },
01799 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPC,            { RT, RA } },
01800 { "azeo",    XO(31,202,1,0), XORB_MASK, POWER,          { RT, RA } },
01801 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC,            { RT, RA } },
01802 { "azeo.",   XO(31,202,1,1), XORB_MASK, POWER,          { RT, RA } },
01803 
01804 { "mtsr",    X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
01805 
01806 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC|B64,        { RS, RA, RB } },
01807 
01808 { "stbx",    X(31,215), X_MASK,         PPC|POWER,      { RS, RA, RB } },
01809 
01810 { "sllq",    XRC(31,216,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
01811 { "sllq.",   XRC(31,216,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
01812 
01813 { "sleq",    XRC(31,217,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
01814 { "sleq.",   XRC(31,217,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
01815 
01816 { "subfme",  XO(31,232,0,0), XORB_MASK, PPC,            { RT, RA } },
01817 { "sfme",    XO(31,232,0,0), XORB_MASK, POWER,          { RT, RA } },
01818 { "subfme.", XO(31,232,0,1), XORB_MASK, PPC,            { RT, RA } },
01819 { "sfme.",   XO(31,232,0,1), XORB_MASK, POWER,          { RT, RA } },
01820 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC,            { RT, RA } },
01821 { "sfmeo",   XO(31,232,1,0), XORB_MASK, POWER,          { RT, RA } },
01822 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC,            { RT, RA } },
01823 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, POWER,          { RT, RA } },
01824 
01825 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01826 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01827 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01828 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01829 
01830 { "addme",   XO(31,234,0,0), XORB_MASK, PPC,            { RT, RA } },
01831 { "ame",     XO(31,234,0,0), XORB_MASK, POWER,          { RT, RA } },
01832 { "addme.",  XO(31,234,0,1), XORB_MASK, PPC,            { RT, RA } },
01833 { "ame.",    XO(31,234,0,1), XORB_MASK, POWER,          { RT, RA } },
01834 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPC,            { RT, RA } },
01835 { "ameo",    XO(31,234,1,0), XORB_MASK, POWER,          { RT, RA } },
01836 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC,            { RT, RA } },
01837 { "ameo.",   XO(31,234,1,1), XORB_MASK, POWER,          { RT, RA } },
01838 
01839 { "mullw",   XO(31,235,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
01840 { "muls",    XO(31,235,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
01841 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
01842 { "muls.",   XO(31,235,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
01843 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
01844 { "mulso",   XO(31,235,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
01845 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
01846 { "mulso.",  XO(31,235,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
01847 
01848 { "mtsrin",  X(31,242), XRA_MASK,       PPC|B32,        { RS, RB } },
01849 { "mtsri",   X(31,242), XRA_MASK,       POWER|B32,      { RS, RB } },
01850 
01851 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { RA, RB } },
01852 
01853 { "stbux",   X(31,247), X_MASK,         PPC|POWER,      { RS, RAS, RB } },
01854 
01855 { "slliq",   XRC(31,248,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
01856 { "slliq.",  XRC(31,248,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
01857 
01858 { "doz",     XO(31,264,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01859 { "doz.",    XO(31,264,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01860 { "dozo",    XO(31,264,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01861 { "dozo.",   XO(31,264,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01862 
01863 { "add",     XO(31,266,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
01864 { "cax",     XO(31,266,0,0), XO_MASK,   POWER,          { RT, RA, RB } },
01865 { "add.",    XO(31,266,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
01866 { "cax.",    XO(31,266,0,1), XO_MASK,   POWER,          { RT, RA, RB } },
01867 { "addo",    XO(31,266,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
01868 { "caxo",    XO(31,266,1,0), XO_MASK,   POWER,          { RT, RA, RB } },
01869 { "addo.",   XO(31,266,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
01870 { "caxo.",   XO(31,266,1,1), XO_MASK,   POWER,          { RT, RA, RB } },
01871 
01872 { "lscbx",   XRC(31,277,0), X_MASK,     POWER|M601,     { RT, RA, RB } },
01873 { "lscbx.",  XRC(31,277,1), X_MASK,     POWER|M601,     { RT, RA, RB } },
01874 
01875 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { RA, RB } },
01876 
01877 { "lhzx",    X(31,279), X_MASK,         PPC|POWER,      { RT, RA, RB } },
01878 
01879 { "icbt",    X(31,262), XRT_MASK,       PPC,            { RA, RB } },
01880 
01881 { "eqv",     XRC(31,284,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01882 { "eqv.",    XRC(31,284,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01883 
01884 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
01885 { "tlbi",    X(31,306), XRTRA_MASK,     POWER,          { RB } },
01886 
01887 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
01888 
01889 { "lhzux",   X(31,311), X_MASK,         PPC|POWER,      { RT, RAL, RB } },
01890 
01891 { "xor",     XRC(31,316,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01892 { "xor.",    XRC(31,316,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01893 
01894 { "mfdcr",   X(31,323), X_MASK,         PPC,            { RT, SPR } },
01895 
01896 { "div",     XO(31,331,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01897 { "div.",    XO(31,331,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01898 { "divo",    XO(31,331,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01899 { "divo.",   XO(31,331,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01900 
01901 { "mfmq",    XSPR(31,339,0), XSPR_MASK, POWER|M601,     { RT } },
01902 { "mfxer",   XSPR(31,339,1), XSPR_MASK, PPC|POWER,      { RT } },
01903 { "mfrtcu",  XSPR(31,339,4), XSPR_MASK, PPC|POWER,      { RT } },
01904 { "mfrtcl",  XSPR(31,339,5), XSPR_MASK, PPC|POWER,      { RT } },
01905 { "mfdec",   XSPR(31,339,6), XSPR_MASK, POWER|M601,     { RT } },
01906 { "mflr",    XSPR(31,339,8), XSPR_MASK, PPC|POWER,      { RT } },
01907 { "mfctr",   XSPR(31,339,9), XSPR_MASK, PPC|POWER,      { RT } },
01908 { "mftid",   XSPR(31,339,17), XSPR_MASK, POWER,         { RT } },
01909 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER,     { RT } },
01910 { "mfdar",   XSPR(31,339,19), XSPR_MASK, PPC|POWER,     { RT } },
01911 { "mfdec",   XSPR(31,339,22), XSPR_MASK, PPC,           { RT } },
01912 { "mfsdr0",  XSPR(31,339,24), XSPR_MASK, POWER,         { RT } },
01913 { "mfsdr1",  XSPR(31,339,25), XSPR_MASK, PPC|POWER,     { RT } },
01914 { "mfsrr0",  XSPR(31,339,26), XSPR_MASK, PPC|POWER,     { RT } },
01915 { "mfsrr1",  XSPR(31,339,27), XSPR_MASK, PPC|POWER,     { RT } },
01916 { "mfsprg",  XSPR(31,339,272), XSPRG_MASK, PPC,         { RT, SPRG } },
01917 { "mfasr",   XSPR(31,339,280), XSPR_MASK, PPC|B64,      { RT } },
01918 { "mfear",   XSPR(31,339,282), XSPR_MASK, PPC,          { RT } },
01919 { "mfpvr",   XSPR(31,339,287), XSPR_MASK, PPC,          { RT } },
01920 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC,       { RT, SPRBAT } },
01921 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC,       { RT, SPRBAT } },
01922 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC,       { RT, SPRBAT } },
01923 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC,       { RT, SPRBAT } },
01924 { "mfspr",   X(31,339), X_MASK,         PPC|POWER,      { RT, SPR } },
01925 
01926 { "lwax",    X(31,341), X_MASK,         PPC|B64,        { RT, RA, RB } },
01927 
01928 { "lhax",    X(31,343), X_MASK,         PPC|POWER,      { RT, RA, RB } },
01929 
01930 { "dccci",   X(31,454), XRT_MASK,       PPC,            { RA, RB } },
01931 
01932 { "abs",     XO(31,360,0,0), XORB_MASK, POWER|M601,     { RT, RA } },
01933 { "abs.",    XO(31,360,0,1), XORB_MASK, POWER|M601,     { RT, RA } },
01934 { "abso",    XO(31,360,1,0), XORB_MASK, POWER|M601,     { RT, RA } },
01935 { "abso.",   XO(31,360,1,1), XORB_MASK, POWER|M601,     { RT, RA } },
01936 
01937 { "divs",    XO(31,363,0,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01938 { "divs.",   XO(31,363,0,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01939 { "divso",   XO(31,363,1,0), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01940 { "divso.",  XO(31,363,1,1), XO_MASK,   POWER|M601,     { RT, RA, RB } },
01941 
01942 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
01943 
01944 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
01945 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
01946 
01947 { "lwaux",   X(31,373), X_MASK,         PPC|B64,        { RT, RAL, RB } },
01948 
01949 { "lhaux",   X(31,375), X_MASK,         PPC|POWER,      { RT, RAL, RB } },
01950 
01951 { "sthx",    X(31,407), X_MASK,         PPC|POWER,      { RS, RA, RB } },
01952 
01953 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
01954 
01955 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
01956 
01957 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
01958 
01959 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
01960 
01961 { "orc",     XRC(31,412,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01962 { "orc.",    XRC(31,412,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01963 
01964 { "sradi",   XS(31,413,0), XS_MASK,     PPC|B64,        { RA, RS, SH6 } },
01965 { "sradi.",  XS(31,413,1), XS_MASK,     PPC|B64,        { RA, RS, SH6 } },
01966 
01967 { "slbie",   X(31,434), XRTRA_MASK,     PPC|B64,        { RB } },
01968 
01969 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
01970 
01971 { "sthux",   X(31,439), X_MASK,         PPC|POWER,      { RS, RAS, RB } },
01972 
01973 { "mr",      XRC(31,444,0), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
01974 { "or",      XRC(31,444,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01975 { "mr.",     XRC(31,444,1), X_MASK,     PPC|POWER,      { RA, RS, RBS } },
01976 { "or.",     XRC(31,444,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
01977 
01978 { "mtdcr",   X(31,451), X_MASK,         PPC,            { SPR, RS } },
01979 
01980 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01981 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01982 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01983 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
01984 
01985 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
01986 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
01987 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
01988 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
01989 
01990 { "mtmq",    XSPR(31,467,0), XSPR_MASK, POWER|M601,     { RS } },
01991 { "mtxer",   XSPR(31,467,1), XSPR_MASK, PPC|POWER,      { RS } },
01992 { "mtlr",    XSPR(31,467,8), XSPR_MASK, PPC|POWER,      { RS } },
01993 { "mtctr",   XSPR(31,467,9), XSPR_MASK, PPC|POWER,      { RS } },
01994 { "mttid",   XSPR(31,467,17), XSPR_MASK, POWER,         { RS } },
01995 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER,     { RS } },
01996 { "mtdar",   XSPR(31,467,19), XSPR_MASK, PPC|POWER,     { RS } },
01997 { "mtrtcu",  XSPR(31,467,20), XSPR_MASK, PPC|POWER,     { RS } },
01998 { "mtrtcl",  XSPR(31,467,21), XSPR_MASK, PPC|POWER,     { RS } },
01999 { "mtdec",   XSPR(31,467,22), XSPR_MASK, PPC|POWER,     { RS } },
02000 { "mtsdr0",  XSPR(31,467,24), XSPR_MASK, POWER,         { RS } },
02001 { "mtsdr1",  XSPR(31,467,25), XSPR_MASK, PPC|POWER,     { RS } },
02002 { "mtsrr0",  XSPR(31,467,26), XSPR_MASK, PPC|POWER,     { RS } },
02003 { "mtsrr1",  XSPR(31,467,27), XSPR_MASK, PPC|POWER,     { RS } },
02004 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK, PPC,         { SPRG, RS } },
02005 { "mtasr",   XSPR(31,467,280), XSPR_MASK, PPC|B64,      { RS } },
02006 { "mtear",   XSPR(31,467,282), XSPR_MASK, PPC,          { RS } },
02007 { "mttbl",   XSPR(31,467,284), XSPR_MASK, PPC,          { RS } },
02008 { "mttbu",   XSPR(31,467,285), XSPR_MASK, PPC,          { RS } },
02009 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
02010 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
02011 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
02012 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
02013 { "mtspr",   X(31,467), X_MASK,         PPC|POWER,      { SPR, RS } },
02014 
02015 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
02016 
02017 { "nand",    XRC(31,476,0), X_MASK,     PPC|POWER,      { RA, RS, RB } },
02018 { "nand.",   XRC(31,476,1), X_MASK,     PPC|POWER,      { RA, RS, RB } },
02019 
02020 { "nabs",    XO(31,488,0,0), XORB_MASK, POWER|M601,     { RT, RA } },
02021 { "nabs.",   XO(31,488,0,1), XORB_MASK, POWER|M601,     { RT, RA } },
02022 { "nabso",   XO(31,488,1,0), XORB_MASK, POWER|M601,     { RT, RA } },
02023 { "nabso.",  XO(31,488,1,1), XORB_MASK, POWER|M601,     { RT, RA } },
02024 
02025 { "divd",    XO(31,489,0,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
02026 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
02027 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC|B64,        { RT, RA, RB } },
02028 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC|B64,        { RT, RA, RB } },
02029 
02030 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
02031 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
02032 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
02033 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
02034 
02035 { "slbia",   X(31,498), 0xffffffff,     PPC|B64,        { 0 } },
02036 
02037 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
02038 
02039 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), PPC|POWER,  { BF } },
02040 
02041 { "clcs",    X(31,531), XRB_MASK,       POWER|M601,     { RT, RA } },
02042 
02043 { "lswx",    X(31,533), X_MASK,         PPC,            { RT, RA, RB } },
02044 { "lsx",     X(31,533), X_MASK,         POWER,          { RT, RA, RB } },
02045 
02046 { "lwbrx",   X(31,534), X_MASK,         PPC,            { RT, RA, RB } },
02047 { "lbrx",    X(31,534), X_MASK,         POWER,          { RT, RA, RB } },
02048 
02049 { "lfsx",    X(31,535), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
02050 
02051 { "srw",     XRC(31,536,0), X_MASK,     PPC,            { RA, RS, RB } },
02052 { "sr",      XRC(31,536,0), X_MASK,     POWER,          { RA, RS, RB } },
02053 { "srw.",    XRC(31,536,1), X_MASK,     PPC,            { RA, RS, RB } },
02054 { "sr.",     XRC(31,536,1), X_MASK,     POWER,          { RA, RS, RB } },
02055 
02056 { "rrib",    XRC(31,537,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02057 { "rrib.",   XRC(31,537,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02058 
02059 { "srd",     XRC(31,539,0), X_MASK,     PPC|B64,        { RA, RS, RB } },
02060 { "srd.",    XRC(31,539,1), X_MASK,     PPC|B64,        { RA, RS, RB } },
02061 
02062 { "maskir",  XRC(31,541,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02063 { "maskir.", XRC(31,541,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02064 
02065 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
02066 
02067 { "lfsux",   X(31,567), X_MASK,         PPC|POWER,      { FRT, RAS, RB } },
02068 
02069 { "mfsr",    X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
02070 
02071 { "lswi",    X(31,597), X_MASK,         PPC,            { RT, RA, NB } },
02072 { "lsi",     X(31,597), X_MASK,         POWER,          { RT, RA, NB } },
02073 
02074 { "sync",    X(31,598), 0xffffffff,     PPC,            { 0 } },
02075 { "dcs",     X(31,598), 0xffffffff,     POWER,          { 0 } },
02076 
02077 { "lfdx",    X(31,599), X_MASK,         PPC|POWER,      { FRT, RA, RB } },
02078 
02079 { "mfsri",   X(31,627), X_MASK,         POWER,          { RT, RA, RB } },
02080 
02081 { "dclst",   X(31,630), XRB_MASK,       POWER,          { RS, RA } },
02082 
02083 { "lfdux",   X(31,631), X_MASK,         PPC|POWER,      { FRT, RAS, RB } },
02084 
02085 { "mfsrin",  X(31,659), XRA_MASK,       PPC|B32,        { RT, RB } },
02086 
02087 { "stswx",   X(31,661), X_MASK,         PPC,            { RS, RA, RB } },
02088 { "stsx",    X(31,661), X_MASK,         POWER,          { RS, RA, RB } },
02089 
02090 { "stwbrx",  X(31,662), X_MASK,         PPC,            { RS, RA, RB } },
02091 { "stbrx",   X(31,662), X_MASK,         POWER,          { RS, RA, RB } },
02092 
02093 { "stfsx",   X(31,663), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
02094 
02095 { "srq",     XRC(31,664,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02096 { "srq.",    XRC(31,664,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02097 
02098 { "sre",     XRC(31,665,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02099 { "sre.",    XRC(31,665,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02100 
02101 { "stfsux",  X(31,695), X_MASK,         PPC|POWER,      { FRS, RAS, RB } },
02102 
02103 { "sriq",    XRC(31,696,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
02104 { "sriq.",   XRC(31,696,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
02105 
02106 { "stswi",   X(31,725), X_MASK,         PPC,            { RS, RA, NB } },
02107 { "stsi",    X(31,725), X_MASK,         POWER,          { RS, RA, NB } },
02108 
02109 { "stfdx",   X(31,727), X_MASK,         PPC|POWER,      { FRS, RA, RB } },
02110 
02111 { "srlq",    XRC(31,728,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02112 { "srlq.",   XRC(31,728,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02113 
02114 { "sreq",    XRC(31,729,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02115 { "sreq.",   XRC(31,729,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02116 
02117 { "stfdux",  X(31,759), X_MASK,         PPC|POWER,      { FRS, RAS, RB } },
02118 
02119 { "srliq",   XRC(31,760,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
02120 { "srliq.",  XRC(31,760,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
02121 
02122 { "lhbrx",   X(31,790), X_MASK,         PPC|POWER,      { RT, RA, RB } },
02123 
02124 { "sraw",    XRC(31,792,0), X_MASK,     PPC,            { RA, RS, RB } },
02125 { "sra",     XRC(31,792,0), X_MASK,     POWER,          { RA, RS, RB } },
02126 { "sraw.",   XRC(31,792,1), X_MASK,     PPC,            { RA, RS, RB } },
02127 { "sra.",    XRC(31,792,1), X_MASK,     POWER,          { RA, RS, RB } },
02128 
02129 { "srad",    XRC(31,794,0), X_MASK,     PPC|B64,        { RA, RS, RB } },
02130 { "srad.",   XRC(31,794,1), X_MASK,     PPC|B64,        { RA, RS, RB } },
02131 
02132 { "rac",     X(31,818), X_MASK,         POWER,          { RT, RA, RB } },
02133 
02134 { "srawi",   XRC(31,824,0), X_MASK,     PPC,            { RA, RS, SH } },
02135 { "srai",    XRC(31,824,0), X_MASK,     POWER,          { RA, RS, SH } },
02136 { "srawi.",  XRC(31,824,1), X_MASK,     PPC,            { RA, RS, SH } },
02137 { "srai.",   XRC(31,824,1), X_MASK,     POWER,          { RA, RS, SH } },
02138 
02139 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
02140 
02141 { "sthbrx",  X(31,918), X_MASK,         PPC|POWER,      { RS, RA, RB } },
02142 
02143 { "sraq",    XRC(31,920,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02144 { "sraq.",   XRC(31,920,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02145 
02146 { "srea",    XRC(31,921,0), X_MASK,     POWER|M601,     { RA, RS, RB } },
02147 { "srea.",   XRC(31,921,1), X_MASK,     POWER|M601,     { RA, RS, RB } },
02148 
02149 { "extsh",   XRC(31,922,0), XRB_MASK,   PPC,            { RA, RS } },
02150 { "exts",    XRC(31,922,0), XRB_MASK,   POWER,          { RA, RS } },
02151 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPC,            { RA, RS } },
02152 { "exts.",   XRC(31,922,1), XRB_MASK,   POWER,          { RA, RS } },
02153 
02154 { "sraiq",   XRC(31,952,0), X_MASK,     POWER|M601,     { RA, RS, SH } },
02155 { "sraiq.",  XRC(31,952,1), X_MASK,     POWER|M601,     { RA, RS, SH } },
02156 
02157 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
02158 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
02159 
02160 { "iccci",   X(31,966), XRT_MASK,       PPC,            { RA, RB } },
02161 
02162 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
02163 
02164 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
02165 
02166 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
02167 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
02168 
02169 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
02170 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
02171 
02172 { "lwz",     OP(32),    OP_MASK,        PPC,            { RT, D, RA } },
02173 { "l",       OP(32),    OP_MASK,        POWER,          { RT, D, RA } },
02174 
02175 { "lwzu",    OP(33),    OP_MASK,        PPC,            { RT, D, RAL } },
02176 { "lu",      OP(33),    OP_MASK,        POWER,          { RT, D, RA } },
02177 
02178 { "lbz",     OP(34),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
02179 
02180 { "lbzu",    OP(35),    OP_MASK,        PPC|POWER,      { RT, D, RAL } },
02181 
02182 { "stw",     OP(36),    OP_MASK,        PPC,            { RS, D, RA } },
02183 { "st",      OP(36),    OP_MASK,        POWER,          { RS, D, RA } },
02184 
02185 { "stwu",    OP(37),    OP_MASK,        PPC,            { RS, D, RAS } },
02186 { "stu",     OP(37),    OP_MASK,        POWER,          { RS, D, RA } },
02187 
02188 { "stb",     OP(38),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
02189 
02190 { "stbu",    OP(39),    OP_MASK,        PPC|POWER,      { RS, D, RAS } },
02191 
02192 { "lhz",     OP(40),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
02193 
02194 { "lhzu",    OP(41),    OP_MASK,        PPC|POWER,      { RT, D, RAL } },
02195 
02196 { "lha",     OP(42),    OP_MASK,        PPC|POWER,      { RT, D, RA } },
02197 
02198 { "lhau",    OP(43),    OP_MASK,        PPC|POWER,      { RT, D, RAL } },
02199 
02200 { "sth",     OP(44),    OP_MASK,        PPC|POWER,      { RS, D, RA } },
02201 
02202 { "sthu",    OP(45),    OP_MASK,        PPC|POWER,      { RS, D, RAS } },
02203 
02204 { "lmw",     OP(46),    OP_MASK,        PPC,            { RT, D, RAM } },
02205 { "lm",      OP(46),    OP_MASK,        POWER,          { RT, D, RA } },
02206 
02207 { "stmw",    OP(47),    OP_MASK,        PPC,            { RS, D, RA } },
02208 { "stm",     OP(47),    OP_MASK,        POWER,          { RS, D, RA } },
02209 
02210 { "lfs",     OP(48),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
02211 
02212 { "lfsu",    OP(49),    OP_MASK,        PPC|POWER,      { FRT, D, RAS } },
02213 
02214 { "lfd",     OP(50),    OP_MASK,        PPC|POWER,      { FRT, D, RA } },
02215 
02216 { "lfdu",    OP(51),    OP_MASK,        PPC|POWER,      { FRT, D, RAS } },
02217 
02218 { "stfs",    OP(52),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
02219 
02220 { "stfsu",   OP(53),    OP_MASK,        PPC|POWER,      { FRS, D, RAS } },
02221 
02222 { "stfd",    OP(54),    OP_MASK,        PPC|POWER,      { FRS, D, RA } },
02223 
02224 { "stfdu",   OP(55),    OP_MASK,        PPC|POWER,      { FRS, D, RAS } },
02225 
02226 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
02227 
02228 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
02229 
02230 { "ld",      DSO(58,0), DS_MASK,        PPC|B64,        { RT, DS, RA } },
02231 
02232 { "ldu",     DSO(58,1), DS_MASK,        PPC|B64,        { RT, DS, RAL } },
02233 
02234 { "lwa",     DSO(58,2), DS_MASK,        PPC|B64,        { RT, DS, RA } },
02235 
02236 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02237 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02238 
02239 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02240 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02241 
02242 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02243 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02244 
02245 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02246 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02247 
02248 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02249 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02250 
02251 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
02252 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
02253 
02254 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02255 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02256 
02257 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02258 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02259 
02260 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02261 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02262 
02263 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02264 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02265 
02266 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
02267 
02268 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
02269 
02270 { "std",     DSO(62,0), DS_MASK,        PPC|B64,        { RS, DS, RA } },
02271 
02272 { "stdu",    DSO(62,1), DS_MASK,        PPC|B64,        { RS, DS, RAS } },
02273 
02274 { "fcmpu",   X(63,0),   X_MASK|(3<<21), PPC|POWER,      { BF, FRA, FRB } },
02275 
02276 { "frsp",    XRC(63,12,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02277 { "frsp.",   XRC(63,12,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02278 
02279 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPC,            { FRT, FRB } },
02280 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
02281 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPC,            { FRT, FRB } },
02282 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
02283 
02284 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPC,            { FRT, FRB } },
02285 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
02286 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPC,            { FRT, FRB } },
02287 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
02288 
02289 { "fdiv",    A(63,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02290 { "fd",      A(63,18,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02291 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02292 { "fd.",     A(63,18,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02293 
02294 { "fsub",    A(63,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02295 { "fs",      A(63,20,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02296 { "fsub.",   A(63,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02297 { "fs.",     A(63,20,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02298 
02299 { "fadd",    A(63,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02300 { "fa",      A(63,21,0), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02301 { "fadd.",   A(63,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
02302 { "fa.",     A(63,21,1), AFRC_MASK,     POWER,          { FRT, FRA, FRB } },
02303 
02304 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPC|POWER2,     { FRT, FRB } },
02305 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPC|POWER2,     { FRT, FRB } },
02306 
02307 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02308 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02309 
02310 { "fmul",    A(63,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
02311 { "fm",      A(63,25,0), AFRB_MASK,     POWER,          { FRT, FRA, FRC } },
02312 { "fmul.",   A(63,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
02313 { "fm.",     A(63,25,1), AFRB_MASK,     POWER,          { FRT, FRA, FRC } },
02314 
02315 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02316 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
02317 
02318 { "fmsub",   A(63,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02319 { "fms",     A(63,28,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02320 { "fmsub.",  A(63,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02321 { "fms.",    A(63,28,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02322 
02323 { "fmadd",   A(63,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02324 { "fma",     A(63,29,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02325 { "fmadd.",  A(63,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02326 { "fma.",    A(63,29,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02327 
02328 { "fnmsub",  A(63,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02329 { "fnms",    A(63,30,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02330 { "fnmsub.", A(63,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02331 { "fnms.",   A(63,30,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02332 
02333 { "fnmadd",  A(63,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02334 { "fnma",    A(63,31,0), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02335 { "fnmadd.", A(63,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
02336 { "fnma.",   A(63,31,1), A_MASK,        POWER,          { FRT,FRA,FRC,FRB } },
02337 
02338 { "fcmpo",   X(63,30),  X_MASK|(3<<21), PPC|POWER,      { BF, FRA, FRB } },
02339 
02340 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  PPC|POWER,      { BT } },
02341 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  PPC|POWER,      { BT } },
02342 
02343 { "fneg",    XRC(63,40,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02344 { "fneg.",   XRC(63,40,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02345 
02346 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
02347 
02348 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  PPC|POWER,      { BT } },
02349 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  PPC|POWER,      { BT } },
02350 
02351 { "fmr",     XRC(63,72,0), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02352 { "fmr.",    XRC(63,72,1), XRA_MASK,    PPC|POWER,      { FRT, FRB } },
02353 
02354 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
02355 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
02356 
02357 { "fnabs",   XRC(63,136,0), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
02358 { "fnabs.",  XRC(63,136,1), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
02359 
02360 { "fabs",    XRC(63,264,0), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
02361 { "fabs.",   XRC(63,264,1), XRA_MASK,   PPC|POWER,      { FRT, FRB } },
02362 
02363 { "mffs",    XRC(63,583,0), XRARB_MASK, PPC|POWER,      { FRT } },
02364 { "mffs.",   XRC(63,583,1), XRARB_MASK, PPC|POWER,      { FRT } },
02365 
02366 { "mtfsf",   XFL(63,711,0), XFL_MASK,   PPC|POWER,      { FLM, FRB } },
02367 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   PPC|POWER,      { FLM, FRB } },
02368 
02369 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02370 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02371 
02372 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02373 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02374 
02375 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02376 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC|B64,        { FRT, FRB } },
02377 
02378 };
02379 
02380 const int powerpc_num_opcodes =
02381   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
02382 

Generated on Fri May 7 21:15:42 2004 by doxygen 1.3.5